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logic gates → 4-bit ALU → CPU execution. Watch gates become a working processor.

5-stage instruction pipeline with hazard detection. Data forwarding, stalls, branch flush visualized. CPI comparison.

Zoom from 300mm silicon wafer → die → standard cells → transistor cross-section. Yield simulation. Electron microscope feel.

Working 8-bit CPU — write assembly, watch fetch/decode/execute with animated data flow. 3 programs counter, Fibonacci, multiply.

Neural net trained in-browser classifies digital signals clock, PWM, SPI, I2C, UART, noise. Oscilloscope display.

CLIP model identifies hand-drawn circuit components. Draw or pick presets — AI classifies AND/OR/resistor/capacitor/op-amp.

Binary/hex/decimal converter with gate-level visualization. Ripple carry adder, shift-and-add multiplier, IEEE 754 floats.

AND, OR, NOT, NAND, XOR, XNOR, NOR — click inputs to toggle, see truth tables, watch signals propagate through gates.

8-bit ALU — click individual bits, choose ADD/SUB/AND/OR/XOR/NOT/SHL/SHR. See binary math + CPU flags (Z/N/C/V).

SR Latch, D Flip-Flop, JK Flip-Flop, 4-bit Counter. Clock pulse, timing diagram, sequential logic explained.

Draw circuits with wire/resistor/capacitor/op-amp tools. Auto-analyze: detect nodes, generate SPICE netlist.

L1/L2 cache sim. Direct-mapped, set-associative. LRU/FIFO. Hit rate tracking.

Visual state machine editor. Add states, transitions. Simulate. Generate Verilog.

Shift-and-add multiplication visualized. Step through partial products bit by bit.

2/3/4 variable K-maps. Click cells, auto-group, minimize Boolean expression.

Registers → L1 → L2 → L3 → RAM → Disk. Access latency animation. Miss penalty calc.

Visualize L1/L2/L3/RAM/Disk with cache replacement policies (LRU, FIFO, Random). Hit rate stats and latency breakdown.

5-stage pipeline (IF/ID/EX/MEM/WB) with hazard detection. Data forwarding, stalls, and CPI comparison.

Visual finite state machine editor. Drag states, draw transitions, simulate inputs, generate Verilog. Mealy/Moore modes.

Generate signals (sine, square, noise), compute FFT, design FIR/IIR filters with interactive pole-zero plot.

Simplified GPU rendering pipeline: vertex shader, rasterizer, fragment shader, framebuffer. Draw a triangle and watch it transform.

Design your own instruction set architecture. Define opcodes, write assembly, execute step-by-step. Compare against MIPS and x86 presets.

Half adder to full adder to ripple carry to carry lookahead. Watch carry propagation gate by gate, highlight critical path, compare gate count and delay.

4-core MESI protocol simulator. Animate state transitions, bus snooping, invalidation. Scenario builder for read/write sequences.

Write Verilog-like HDL, simulate combinational and sequential logic, view waveform timing diagrams. Pre-loaded examples: SR latch, D flip-flop, counter, traffic light FSM.

Dynamic power (CV2f), static leakage, thermal model. Frequency vs power curves, technology node comparison (90nm to 5nm), historical MHz vs Watts trend.