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Chip simulations

Chip Challenges

Test your digital logic and chip design skills. Build circuits from fundamental gates, compute ALU operations, construct counters, and generate netlists.

Active Challenges

Hard

Build a Full Adder from NAND Gates Only

Construct a complete full adder (sum + carry) using nothing but NAND gates. The universal gate challenge — prove NAND is functionally complete.

Digital Logic | ~5 min
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Easy

Compute 42 XOR 15 in the ALU

Load operands into the ALU simulator, select the XOR operation, and verify the result. Understand how arithmetic logic units process bitwise operations.

CPU Architecture | ~2 min
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Medium

Build a 4-bit Counter and Reach 15

Wire up four flip-flops into a synchronous binary counter. Clock the circuit until the output reads 1111 (15 in decimal).

Sequential Logic | ~4 min
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Medium

Draw a Voltage Divider and Generate Its Netlist

Place resistors to form a voltage divider circuit, then export the SPICE netlist. Verify the output voltage matches the expected ratio.

Analog Circuits | ~3 min
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Personal Records

Coming soon — your best times and scores will be tracked here using local storage. Complete challenges to start building your record.