Simple Verilog Simulator

Write Verilog-like HDL, simulate combinational + sequential logic, view waveforms

module editorReady

Clock Cycles

Current Cycle: 0

wire name;
reg name = 0;
assign out = a & b;
always @(posedge clk) {
if (cond) reg = val;
else reg = val2;
}
Operators: & | ^ ~ + - == != < >