Chip Design Institute

Fundamentals

What is Chip Design?

Chip design (VLSI design) is the process of creating integrated circuits — from defining architecture and writing hardware description languages (Verilog/VHDL) to physical layout and fabrication. Modern chips contain billions of transistors and power everything from smartphones to data centers.

Key Concepts

Boolean Algebra — the mathematical foundation of digital logic. AND, OR, NOT, XOR gates implement Boolean functions in silicon.
Flip-Flops & Latches — sequential storage elements. D flip-flops store one bit, triggered by clock edges. Foundation of registers and memory.
Finite State Machines — Mealy and Moore machines model sequential logic. States, transitions, outputs. Used everywhere from protocol controllers to CPUs.
Pipelining — break computation into stages, process multiple instructions simultaneously. Increases throughput at the cost of latency.
Caches — small, fast memory close to the CPU. L1/L2/L3 hierarchy. Spatial and temporal locality. Cache coherence in multicore.
RISC-V ISA — open-source instruction set architecture. Base integer ISA (RV32I/RV64I) plus standard extensions (M, A, F, D, C). The Linux of hardware.

Abstraction Layers

System architecture → microarchitecture → RTL (Register Transfer Level) → gate-level netlist → transistor-level → physical layout → fabrication.
RTL is written in Verilog or VHDL, synthesized to gates by tools like Yosys, then placed and routed into a physical chip layout.
FPGAs let you prototype designs on reconfigurable hardware before committing to an ASIC (application-specific integrated circuit) tape-out.
Modern SoCs (System-on-Chip) integrate CPU cores, GPU, memory controllers, I/O, and accelerators on a single die.

Free Courses

MIT 6.004: Computation Structures

From gates to processors. Digital logic, computer architecture, pipelining, caches, virtual memory. The gold standard intro course.

MIT OpenCourseWare | Free | Intermediate

Nand2Tetris

Build a complete computer from NAND gates. Hardware, assembler, VM, compiler, OS — all from scratch. The best way to understand computers.

Hebrew University | Free | Beginner

Coursera: Digital Systems (UAB)

Fundamentals of digital design. Combinational and sequential logic, Verilog, FPGA implementation. Free to audit.

Autonomous University of Barcelona | Free audit | Beginner

edX: FPGA Design Courses

Multiple FPGA courses from universities. Learn Verilog/VHDL, synthesis, timing analysis, and FPGA implementation.

edX | Free audit | Intermediate

ZipCPU Tutorials

Practical Verilog tutorials and FPGA design. Formal verification, bus protocols, DDR memory controllers. Excellent blog.

Free | Intermediate to Advanced

RISC-V Specifications

Official RISC-V ISA specifications. Unprivileged, privileged, and debug specs. The foundation for open-source CPU design.

RISC-V International | Free | Reference

Textbooks

Harris & Harris: Digital Design and Computer Architecture — Best intro textbook. Covers combinational/sequential logic, Verilog/SystemVerilog, MIPS and RISC-V architectures.
Patterson & Hennessy: Computer Organization and Design (RISC-V Edition) — Classic textbook on computer architecture. Pipeline, memory hierarchy, parallelism. RISC-V edition is the latest.
Hennessy & Patterson: Computer Architecture — A Quantitative Approach — Graduate-level. Instruction-level parallelism, memory, multiprocessors, warehouse-scale computing.
Weste & Harris: CMOS VLSI Design — Comprehensive treatment of CMOS circuit and layout design. From transistors to systems.
Nisan & Schocken: The Elements of Computing Systems — The Nand2Tetris textbook. Build a computer, assembler, VM, compiler, and OS from first principles.

Key Research Papers

Moore (1965): Cramming More Components

Predicted transistor count doubles every two years. This observation drove the semiconductor industry for six decades and shaped modern computing.

Gordon Moore | Electronics Magazine

Dennard et al (1974): Scaling Theory

Dennard scaling: as transistors shrink, voltage and current scale proportionally, keeping power density constant. Broke down around 2006 (power wall).

Robert Dennard | IBM | IEEE JSSC

Waterman et al (2014): The RISC-V ISA

The RISC-V instruction set architecture specification. Clean, modular, open-source ISA. Now used in billions of chips.

UC Berkeley | RISC-V Foundation

Patterson & Ditzel (1980): The Case for RISC

Argued for Reduced Instruction Set Computers over CISC. Simpler instructions, faster clock, better pipelining. Spawned SPARC, MIPS, ARM, RISC-V.

Patterson & Ditzel | ACM SIGARCH

Esmaeilzadeh et al (2011): Dark Silicon

Showed that power constraints mean most transistors on future chips must be powered off ("dark"). Motivated specialization and accelerators.

ISCA 2011 | Best Paper

Jouppi et al (2017): TPU — In-Datacenter Performance

Google's Tensor Processing Unit. Custom ASIC for neural network inference. 15-30x faster than GPUs for ML workloads. Launched the AI accelerator era.

Google | ISCA 2017

Open-Source Tools

Verilator

Fastest open-source Verilog/SystemVerilog simulator. Compiles RTL to optimized C++/SystemC. Used in industry and academia.

C++ | 5K+ stars | LGPL

Yosys

Open-source synthesis suite. Verilog RTL to gate-level netlist. Supports FPGA and ASIC flows. Foundation of the open-source EDA ecosystem.

C++ | 3K+ stars | ISC License

GHDL

Open-source VHDL simulator. Supports VHDL-87/93/2002/2008. Synthesis via ghdl-yosys-plugin. Complete VHDL workflow.

Ada / C | 2K+ stars | GPL

OpenROAD

Complete open-source RTL-to-GDS flow. Floorplanning, placement, CTS, routing. Autonomous, no-human-in-the-loop chip design.

C++ | DARPA-funded | BSD

KiCad

Open-source PCB design suite. Schematic capture, PCB layout, 3D viewer, Gerber output. Professional-quality, completely free.

C++ | CERN-origin | GPL

Icarus Verilog

Open-source Verilog simulation and synthesis tool. Lightweight, fast compilation, good for learning and small projects.

C++ | 2.5K+ stars | GPL

Industry & Hardware

AMD

Ryzen CPUs, EPYC servers, Radeon GPUs. Chiplet architecture (Zen). Major x86 competitor. Acquired Xilinx (FPGAs).

CPUs / GPUs / FPGAs

Intel

World's largest chipmaker. Core/Xeon CPUs, Intel Foundry Services. Pioneered x86, pushing Intel 18A process node.

CPUs / Foundry

TSMC

Taiwan Semiconductor Manufacturing Company. World's largest foundry. Manufactures chips for Apple, AMD, NVIDIA, Qualcomm. Leading-edge nodes (3nm, 2nm).

Foundry | Market leader

NVIDIA

GPU computing leader. GeForce (gaming), A100/H100 (AI training), Grace-Hopper (superchips). CUDA ecosystem dominates ML/HPC.

GPUs / AI accelerators

Lattice Semiconductor

Low-power FPGAs. iCE40 (open-source toolchain via Yosys+nextpnr), ECP5, CrossLink-NX. Accessible FPGA development.

FPGAs | Low-power

Raspberry Pi Pico

RP2040 microcontroller. Dual-core ARM Cortex-M0+, PIO (Programmable I/O) state machines. $4. Great for learning embedded design.

Microcontroller | $4 | Open docs

Reference

Digital Logic

Boolean Algebra — AND (a&b), OR (a|b), NOT (!a), XOR (a^b). De Morgan's laws: !(a&b) = !a|!b. Karnaugh maps for minimization.
Combinational Logic — multiplexers, decoders, encoders, adders (ripple-carry, carry-lookahead), ALUs. Output depends only on current inputs.
Sequential Logic — flip-flops (D, JK, T), registers, counters, shift registers. Output depends on inputs AND current state (clock-driven).
FSMs — Finite State Machines: Moore (output = f(state)) or Mealy (output = f(state, input)). State diagrams, state tables, encoding.

Computer Architecture

Pipelining — IF→ID→EX→MEM→WB. Hazards: data (forwarding/stalling), control (branch prediction), structural (resource conflicts).
Caches — direct-mapped, set-associative, fully-associative. Write-back vs write-through. Replacement: LRU, FIFO, random.
Branch Prediction — static (always taken), dynamic (BHT, 2-bit saturating counters), BTB, tournament predictors.
Out-of-Order Execution — Tomasulo's algorithm, reservation stations, reorder buffer (ROB), register renaming. ILP extraction.

RISC-V

Base ISA — RV32I (32-bit integer): 47 instructions. Load/store architecture, 32 registers (x0=0), 6 instruction formats (R/I/S/B/U/J).
Standard Extensions — M (multiply/divide), A (atomic), F/D (single/double float), C (compressed 16-bit instructions), V (vector).
Privileged Spec — Machine (M), Supervisor (S), User (U) modes. CSRs, interrupts, virtual memory (Sv39/Sv48 page tables).
Ecosystem — BOOM, Rocket (UCB generators), CVA6, PicoRV32, VexRiscv. Linux, Zephyr, FreeRTOS support.