Cache Simulator
Memory access simulation with hit/miss tracking and replacement policies
Cache Lines:
4
8
16
Associativity:
Direct-Mapped
2-Way
4-Way
Fully Assoc.
Replacement:
LRU
FIFO
Random
Address:
Access
Sequential
Random 20
Reset
Hits:
0
Misses:
0
Hit Rate:
0%
Total:
0