Chip to CPU Pipeline

Logic Gates → ALU → CPU Instruction Execution

Step 1
Logic Gates
Waiting
→
Step 2
4-bit ALU
Waiting
→
Step 3
CPU Execute
Waiting
1
Logic Gates → Half Adder → Full Adder

Digital logic starts with gates. Select any gate to see its truth table. Then we combine XOR (for sum) and AND (for carry) into a half adder -- the fundamental arithmetic building block. Two half adders plus an OR gate make a full adder that handles carry-in.

AND
OR
XOR
NAND
NOR
XNOR
↓
Full adders chain into a ripple-carry ALU
2
4-bit Ripple-Carry ALU

Chain 4 full adders (each built from 2 half adders). The carry output of each bit feeds into the carry input of the next -- this "ripple" gives the adder its name. The ALU also supports SUB (via 2's complement), AND, OR, and XOR.

↓
ALU embedded in a CPU executes instructions
3
CPU Instruction Execution

A minimal CPU with 4 general-purpose registers (R0-R3), a program counter (PC), flags (Zero, Carry), and the ALU from Step 2. Watch each instruction go through the classic pipeline: Fetch → Decode → Execute → Writeback.