Verilog / HDL

HDL Overview

A Hardware Description Language (HDL) describes the structure and behavior of digital circuits. Unlike software programming languages, HDL statements execute concurrently, modeling the parallel nature of hardware. The two dominant HDLs are Verilog and VHDL.

Verilog

Created by Phil Moorby and Prabhu Goel at Gateway Design Automation in 1984. Acquired by Cadence, then donated to IEEE in 1995 (IEEE 1364). C-like syntax. Dominant in the US and Asia. Extended to SystemVerilog (IEEE 1800) in 2005, adding object-oriented verification features, assertions, and improved synthesis constructs.

VHDL

VHSIC Hardware Description Language. Created under a U.S. Department of Defense program in 1983. IEEE 1076. Ada-like syntax — strongly typed, verbose, explicit. Dominant in Europe and defense/aerospace. More verbose than Verilog but catches more errors at compile time.

Modern Alternatives

• Chisel — Scala-embedded HDL from UC Berkeley. Generates Verilog. Used to build RISC-V cores (Rocket, BOOM). Powerful parameterization via Scala's type system.
• Amaranth (formerly nMigen) — Python-embedded HDL. Clean, Pythonic API. Generates Verilog for simulation and synthesis. Popular in the open-source FPGA community.
• SpinalHDL — Scala-based HDL (independent of Chisel). Strong type checking, good for complex designs. VexRiscv (RISC-V core) is written in SpinalHDL.
• Clash — Haskell-embedded HDL. Functional programming paradigm for hardware. Leverages Haskell's type system to prevent common errors at compile time.

Syntax Basics

Data Types

• wire — continuous assignment. Represents a combinational connection. Cannot store state. Driven by assign statements or module outputs. Think of it as a physical wire.
• reg — can be assigned inside procedural blocks (always, initial). Despite the name, doesn't necessarily synthesize to a register — it can be combinational if assigned in a combinational always block. In SystemVerilog, use logic instead to avoid confusion.
• Bit widths — declared as [MSB:LSB]. Example: wire [7:0] data; is an 8-bit bus. Default is 1 bit. Bit select: data[3]. Range select: data[7:4].
• Number literals — format: <width>'<base><value>. Examples: 8'hFF (8-bit hex), 4'b1010 (4-bit binary), 32'd100 (32-bit decimal). Underscore for readability: 32'hDEAD_BEEF.
• 4-value logic — Verilog uses four values: 0, 1, X (unknown/don't-care), Z (high-impedance/tri-state). X propagates through logic; Z models undriven wires and tri-state buffers.

Operators

• Bitwise — & (AND), | (OR), ^ (XOR), ~ (NOT)
• Logical — &&, ||, ! (return 1-bit result)
• Reduction — &data (AND all bits), |data (OR all bits), ^data (XOR all bits / parity)
• Shift — <<, >> (logical), <<<, >>> (arithmetic, sign-extending)
• Concatenation — {a, b, c} joins signals. Replication: {4{1'b0}} = 4'b0000
• Conditional (ternary) — sel ? a : b synthesizes to a multiplexer

Modules & Hierarchy

The module is the fundamental building block in Verilog. It encapsulates a piece of hardware with defined inputs and outputs. Designs are built hierarchically: a top-level module instantiates sub-modules, which instantiate smaller sub-modules, down to primitive gates.

Module Declaration

module adder #(
  parameter WIDTH = 8       // parameterized width
)(
  input  wire [WIDTH-1:0] a,
  input  wire [WIDTH-1:0] b,
  input  wire             cin,
  output wire [WIDTH-1:0] sum,
  output wire             cout
);
  assign {cout, sum} = a + b + cin;
endmodule

Module Instantiation

// Named port connection (recommended)
adder #(.WIDTH(16)) u_adder16 (
  .a    (operand_a),
  .b    (operand_b),
  .cin  (carry_in),
  .sum  (result),
  .cout (carry_out)
);

Parameters and Generate

• parameter — compile-time constants. Override with #(.WIDTH(16)) at instantiation. Makes modules reusable.
• localparam — like parameter but cannot be overridden from outside. Use for derived constants.
• generate — create replicated or conditional hardware. genvar i; generate for (i=0; i<N; i=i+1) begin ... end endgenerate creates N copies of a sub-circuit.

Always Blocks

Always blocks are procedural blocks that describe both combinational and sequential logic. The sensitivity list determines when the block executes.

Combinational Always Block

// Verilog-2001: use @(*)
always @(*) begin
  case (sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
    2'b11: out = d;
  endcase
end

// SystemVerilog: always_comb (preferred)
always_comb begin
  unique case (sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
    2'b11: out = d;
  endcase
end

Use blocking assignments (=) in combinational blocks. The always_comb keyword in SystemVerilog enforces that the block describes combinational logic and triggers at time 0.

Sequential Always Block

// Flip-flop with synchronous reset
always @(posedge clk) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

// SystemVerilog: always_ff (preferred)
always_ff @(posedge clk) begin
  if (rst)
    q <= '0;
  else
    q <= d;
end

Use non-blocking assignments (<=) in sequential blocks. This ensures all flip-flops sample their inputs simultaneously at the clock edge, modeling the parallel nature of hardware correctly.

Blocking vs Non-Blocking

• Blocking (=) — executes sequentially within the block. Use for combinational logic. Statement N+1 sees the result of statement N immediately.
• Non-blocking (<=) — schedules the assignment for the end of the current time step. Use for sequential logic (flip-flops). All RHS values are read simultaneously (old values), then all LHS are updated together.
• The cardinal rule — never mix blocking and non-blocking assignments to the same signal. Never use blocking in sequential blocks or non-blocking in combinational blocks. Violating this causes simulation-synthesis mismatches.

Testbenches

A testbench is a Verilog module with no ports that instantiates the design under test (DUT), drives stimuli, and checks outputs. Testbenches are not synthesizable — they use the full language including delays, file I/O, and system tasks.

Basic Testbench Structure

module tb_adder;
  reg  [7:0] a, b;
  reg        cin;
  wire [7:0] sum;
  wire       cout;

  // Instantiate the DUT
  adder #(.WIDTH(8)) dut (
    .a(a), .b(b), .cin(cin),
    .sum(sum), .cout(cout)
  );

  initial begin
    // Dump waveforms
    $dumpfile("adder.vcd");
    $dumpvars(0, tb_adder);

    // Test case 1
    a = 8'd100; b = 8'd50; cin = 0;
    #10;
    if (sum !== 8'd150 || cout !== 0)
      $error("Test 1 FAILED");

    // Test case 2: overflow
    a = 8'd200; b = 8'd100; cin = 0;
    #10;
    if ({cout, sum} !== 9'd300)
      $error("Test 2 FAILED");

    $display("All tests passed");
    $finish;
  end
endmodule

Clock Generation

reg clk = 0;
always #5 clk = ~clk;  // 100 MHz clock (10ns period)

SystemVerilog Verification

• Assertions — assert property (@(posedge clk) req |-> ##[1:3] ack); — verify temporal properties. Immediate assertions for simple checks, concurrent assertions for protocol verification.
• Covergroups — track which values/transitions have been exercised. Functional coverage ensures the testbench has tested the interesting cases.
• Constrained random — class transaction; rand bit [7:0] data; constraint c { data inside {[0:100]}; } endclass — randomly generate stimuli within constraints. Much more thorough than directed testing.
• UVM (Universal Verification Methodology) — industry-standard framework for building reusable, modular testbenches. Agents, drivers, monitors, scoreboards. Overkill for small designs but essential for SoC verification.

Simulation

Simulation runs the Verilog design as a software model, checking functionality before committing to hardware. There are two main types: event-driven simulation and cycle-based simulation.

Event-Driven Simulation

• Processes events (signal changes) in timestamp order. Models exact timing including propagation delays.
• Tools: Icarus Verilog (open-source, good for learning), ModelSim/Questa (industry standard from Siemens EDA), VCS (Synopsys, fastest commercial simulator), Xcelium (Cadence).
• Verilog's simulation semantics define an event queue with regions: active (blocking assignments, continuous assignments), inactive (#0 delays), NBA (non-blocking assignment updates), monitor ($monitor), and future events.

Cycle-Based Simulation

• Only evaluates at clock edges, ignoring intra-cycle timing. Much faster for synchronous designs (10-100x faster than event-driven).
• Verilator — open-source, compiles Verilog/SystemVerilog to optimized C++. The fastest open-source simulator. Lint mode catches many RTL issues. Supports multithreading. Used by Google, Western Digital, and many others for large designs.
• Trade-off: doesn't model glitches, setup/hold violations, or asynchronous behavior. Great for functional verification; timing verification needs gate-level simulation with SDF back-annotation.

Waveform Viewing

Simulations dump signal values to VCD (Value Change Dump) or FST (Fast Signal Trace) files. View with GTKWave (open-source, VCD/FST) or Surfer (modern, Rust-based). Waveform debugging is the primary way to diagnose hardware design bugs — you can see every signal at every point in time.

Synthesis

Synthesis converts RTL code into a gate-level netlist — a circuit composed of standard cells (NAND, NOR, DFF, etc.) from a target library. The synthesizer optimizes for area, timing, and power.

Synthesizable vs Non-Synthesizable

• Synthesizable — assign, always @(*), always @(posedge clk), if/else, case, arithmetic operators, concatenation, generate blocks, instantiations.
• Not synthesizable — #delay, initial blocks, $display/$finish, file I/O, fork/join, wait statements, most real-number arithmetic. These are simulation-only constructs for testbenches.

Synthesis Tools

• Yosys — open-source synthesis. Supports Verilog-2005 and partial SystemVerilog. FPGA flows (iCE40, ECP5, Xilinx) and ASIC flows (with Liberty cell libraries). Foundation of the open-source EDA stack.
• Synopsys Design Compiler — the gold standard for ASIC synthesis. Used by virtually every chip company. Proprietary, expensive.
• Cadence Genus — Cadence's synthesis tool. Competitive with Design Compiler. Part of the Cadence digital flow.
• Vivado Synthesis — Xilinx/AMD's built-in synthesis for their FPGAs. Part of the Vivado Design Suite.
• Quartus Synthesis — Intel/Altera's synthesis for their FPGAs. Part of Quartus Prime.

Timing Constraints

You must tell the synthesis tool the target clock frequency. Synopsys Design Constraints (SDC) format: create_clock -period 10 [get_ports clk] (100 MHz). The tool optimizes the circuit to meet this timing, reporting slack (positive = met, negative = violated). Input/output delays, multicycle paths, and false paths are also specified in SDC.

Common Patterns

Shift Register

always_ff @(posedge clk)
  if (rst)  shift_reg <= '0;
  else      shift_reg <= {shift_reg[N-2:0], data_in};

Counter with Enable and Load

always_ff @(posedge clk)
  if (rst)        count <= '0;
  else if (load)  count <= load_val;
  else if (en)    count <= count + 1;

FSM (Finite State Machine)

typedef enum logic [1:0] {
  IDLE, ACTIVE, DONE
} state_t;

state_t state, next_state;

// State register
always_ff @(posedge clk)
  if (rst) state <= IDLE;
  else     state <= next_state;

// Next-state logic (combinational)
always_comb begin
  next_state = state;  // default: hold
  unique case (state)
    IDLE:   if (start) next_state = ACTIVE;
    ACTIVE: if (done)  next_state = DONE;
    DONE:              next_state = IDLE;
  endcase
end

// Output logic
assign busy = (state == ACTIVE);

Synchronizer (Clock Domain Crossing)

// Two-flop synchronizer for single-bit signals
reg [1:0] sync_reg;
always_ff @(posedge clk_dst)
  sync_reg <= {sync_reg[0], async_signal};
wire synced = sync_reg[1];

Edge Detector

reg signal_d;
always_ff @(posedge clk) signal_d <= signal;
wire rising_edge  = signal & ~signal_d;
wire falling_edge = ~signal & signal_d;

Parameterized Multiplexer

module mux #(
  parameter INPUTS = 4,
  parameter WIDTH  = 8
)(
  input  wire [$clog2(INPUTS)-1:0] sel,
  input  wire [WIDTH-1:0]          in [INPUTS],
  output wire [WIDTH-1:0]          out
);
  assign out = in[sel];
endmodule

Gotchas

Common mistakes that cause simulation-synthesis mismatches, silent bugs, or synthesis failures.

Latches from Incomplete Assignments

• If a combinational always block doesn't assign a signal in every path, the synthesizer infers a latch (the signal holds its old value). This is almost always a bug.
• Fix: assign a default value at the top of the block, or cover all cases in case/if statements. In SystemVerilog, unique case and always_comb provide warnings.

Sensitivity List Errors

• In Verilog-2001, forgetting a signal in always @(...) causes simulation to not trigger when that signal changes, but synthesis ignores the sensitivity list and infers the correct logic. Result: simulation and hardware behave differently.
• Fix: always use @(*) for combinational logic, or better yet, always_comb in SystemVerilog.

Blocking in Sequential Blocks

• Using = instead of <= in always @(posedge clk) can cause race conditions. Two flip-flops that should both sample the same value at the clock edge may instead form a dependency chain.
• Fix: always use <= in clocked blocks. Lint tools (Verilator, Spyglass) will flag this.

Multi-Driven Signals

• Assigning the same reg in two different always blocks is illegal (undefined behavior). The synthesizer may pick one, both, or error out. Simulation gives X.
• Fix: each signal should be driven from exactly one always block or one assign statement.

Integer Overflow

• Verilog silently truncates results to the width of the LHS. wire [7:0] sum = 8'd200 + 8'd100; gives 8'd44 (300 mod 256). No warning.
• Fix: use explicit widths and carry bits: wire [8:0] sum = a + b; to capture the carry.

Signed vs Unsigned

• By default, all Verilog signals are unsigned. Arithmetic right shift (>>>) only sign-extends if the operand is declared signed. Mixing signed and unsigned operands in an expression makes the entire expression unsigned.
• Fix: explicitly declare signed signals: wire signed [7:0] temp; or use $signed() casts.

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