The open-source instruction set architecture reshaping the semiconductor industry. Free to implement, free to extend, designed from clean-slate principles by UC Berkeley researchers.
RISC-V (pronounced "risk-five") is an open, free instruction set architecture (ISA) that originated at UC Berkeley in 2010. Created by Krste Asanovic, Andrew Waterman, and Yunsup Lee, it was the fifth RISC ISA designed at Berkeley (after RISC-I, RISC-II, SOAR, and SPUR). Unlike ARM or x86, RISC-V is not owned by any company — it is governed by RISC-V International, a non-profit foundation with 4,000+ member organizations.
RV32I is the base 32-bit integer instruction set. It defines 47 instructions, 32 integer registers (x0-x31, each 32 bits wide), and a 32-bit program counter. Register x0 is hardwired to zero — reads always return 0, writes are discarded. This simplifies instruction encoding and eliminates the need for a separate "move" instruction (use add rd, rs, x0).
ADD, SUB, ADDI (add immediate). No flags register — comparisons are done with branch instructions or SLT (Set Less Than).AND, OR, XOR, ANDI, ORI, XORI.SLL (shift left logical), SRL (shift right logical), SRA (shift right arithmetic). Immediate variants: SLLI, SRLI, SRAI.SLT (set less than, signed), SLTU (unsigned), SLTI, SLTIU. Sets destination register to 1 if condition holds, 0 otherwise.LW (load word), LH/LHU (load halfword signed/unsigned), LB/LBU (load byte). SW, SH, SB for stores. Load/store architecture: only these instructions access memory.BEQ (branch if equal), BNE (not equal), BLT/BLTU (less than signed/unsigned), BGE/BGEU (greater or equal). PC-relative, 12-bit signed offset (range: -4096 to +4094 bytes).JAL (jump and link: saves return address to rd), JALR (jump and link register: indirect jump). Used for function calls and returns.LUI (load upper immediate: loads a 20-bit constant into the upper 20 bits of rd), AUIPC (add upper immediate to PC). Together with ADDI, these construct arbitrary 32-bit constants and addresses.ECALL (system call), EBREAK (debugger breakpoint), FENCE (memory ordering).The 64-bit variant. Registers are 64 bits wide. Adds word-sized variants: ADDW, SUBW, SLLW, SRLW, SRAW (operate on the lower 32 bits and sign-extend the result), plus LWU (load word unsigned) and LD/SD (load/store doubleword). RV64I is the target for Linux-capable application processors.
| Extension | Name | Description |
|---|---|---|
| M | Multiply/Divide | MUL, MULH, MULHU, MULHSU, DIV, DIVU, REM, REMU. Hardware integer multiplication and division. Essential for general-purpose computing. |
| A | Atomic | LR (Load-Reserved), SC (Store-Conditional), and AMO (Atomic Memory Operations: AMOSWAP, AMOADD, AMOAND, AMOOR, AMOXOR, AMOMAX, AMOMIN). For multi-core synchronization, mutexes, lock-free data structures. |
| F | Single-Precision Float | 32 floating-point registers (f0-f31). FADD.S, FSUB.S, FMUL.S, FDIV.S, FSQRT.S, FMA (fused multiply-add), comparisons, conversions. IEEE 754 compliant. |
| D | Double-Precision Float | Extends F to 64-bit doubles. Same operations with .D suffix. f registers are 64 bits wide. Requires F extension. |
| C | Compressed | 16-bit encodings for common instructions. Reduces code size by 25-30% with minimal hardware cost. A 16-bit C instruction maps to exactly one 32-bit base instruction. Mixed 16/32-bit instruction stream. |
| V | Vector | Scalable vector extension. Variable-length vectors (implementation chooses VLEN: 128-65536 bits). VADD, VMUL, VFMA, masked operations, strided/indexed loads. For SIMD, machine learning, DSP. |
| Zicsr | CSR Instructions | CSRRW, CSRRS, CSRRC (read/write/set/clear Control and Status Registers). Access performance counters, interrupt configuration, etc. |
| Zifencei | Instruction Fence | FENCE.I instruction for synchronizing instruction and data memory. Needed for self-modifying code, JIT compilers. |
| B | Bit Manipulation | Zba (address generation), Zbb (basic bit manipulation: CLZ, CTZ, CPOP, REV8, ORC.B), Zbc (carry-less multiply), Zbs (single-bit operations). Ratified 2024. |
RV32G = RV32IMAFDZicsr_Zifencei — the "general-purpose" ISA combining the base integer ISA with multiply, atomics, single and double float, CSR access, and instruction fence. This is the standard target for Linux-capable processors. RV64G is the 64-bit equivalent.
RISC-V explicitly reserves opcode space for custom extensions (four major opcodes reserved). Companies can add domain-specific instructions without conflicting with standard extensions. Examples: Qualcomm Hexagon-style VLIW extensions, AI accelerator instructions, cryptographic instructions. Custom extensions are a key advantage over ARM and x86, where adding instructions requires vendor approval.
RISC-V uses 6 instruction formats, all 32 bits wide. The opcode field (bits 6:0) is always in the same position. Source registers (rs1, rs2) and destination register (rd) are always in the same bit positions when present. This regularity simplifies decode hardware.
[funct7 | rs2 | rs1 | funct3 | rd | opcode]. Used for ADD, SUB, AND, OR, SLL, SLT, etc.[imm[11:0] | rs1 | funct3 | rd | opcode]. 12-bit signed immediate. Used for ADDI, LW, JALR, etc.[imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode]. Immediate split across two fields (no rd needed for stores).[imm[12|10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode]. 12-bit signed offset, always even (bit 0 implicitly 0). Allows +/- 4 KiB range.[imm[31:12] | rd | opcode]. 20-bit immediate placed in upper bits. Used for LUI, AUIPC.[imm[20|10:1|11|19:12] | rd | opcode]. 20-bit signed offset. JAL can jump +/- 1 MiB.The consistent register field positions (rs1 at bits 19:15, rs2 at bits 24:20, rd at bits 11:7) allow the register file to be read before the instruction is fully decoded. The immediate encoding places the sign bit always at bit 31 for fast sign-extension. These seemingly minor choices significantly simplify high-performance pipeline implementations.
The RISC-V privileged specification defines the machine modes, interrupt handling, virtual memory, and system-level features needed to run operating systems.
The SBI is the firmware interface between S-mode (OS kernel) and M-mode (firmware). It provides standardized services: console I/O, timer, IPI (inter-processor interrupt), remote fence, HSM (hart state management), and PMU (performance monitoring). OpenSBI is the reference open-source SBI implementation. Analogous to BIOS/UEFI services in the x86 world.
RISC-V defines a standard debug interface: debug module (DM), debug transport module (DTM), and trigger module. Supports external debug (via JTAG) and self-hosted debug (ebreak). GDB connects via OpenOCD. Hardware breakpoints (up to implementation-defined count) and single-stepping are specified.
In-order, 5-stage pipeline. Written in Chisel (Scala). The reference RISC-V implementation from UC Berkeley. Configurable, well-tested, and silicon-proven.
Berkeley Out-of-Order Machine. Superscalar, out-of-order, speculative. Written in Chisel. Research-grade implementation competitive with commercial cores.
6-stage, single-issue, in-order pipeline. SystemVerilog. Linux-capable. Maintained by OpenHW Group. Used in academic and industrial research.
Highly configurable RISC-V core. Written in SpinalHDL. From tiny (RV32E, 400 LUTs) to Linux-capable (RV32IMA, MMU). FPGA-optimized.
Tiny RISC-V core (RV32IMC). ~2000 lines of Verilog. Optimized for area (750-2000 LUTs). No pipeline — multicycle. Great for learning and tiny FPGA projects.
Full-featured RISC-V processor in VHDL. RV32/RV64, M/S/U modes, MMU, FPU, peripherals included. Targets any FPGA. Excellent documentation.
Official ISA specifications. Unprivileged spec, privileged spec, debug spec, and extension ratification status. The authoritative source.
Patterson & Waterman's practical introduction to RISC-V. Concise, well-written, covers the ISA and its design rationale. Available as free PDF.
The reference functional RISC-V ISA simulator. Written in C++. Supports RV32/RV64, all standard extensions, and interactive debug mode.
GCC, binutils, glibc/newlib for RISC-V. Cross-compiler for bare-metal (riscv64-unknown-elf) and Linux (riscv64-unknown-linux-gnu) targets.
Free RISC-V courses and documentation from SiFive. Core architecture guides, software tutorials, and development board guides.
Comprehensive RISC-V reference. Instruction encoding tables, CSR documentation, extension summaries. Invaluable quick reference.